This invention relates to a display control circuit which effectively refreshes memory cells of a video RAM constituted by a dynamic RAM.
A CRT control device includes a video RAM. If the video RAM is a dynamic RAM, it is necessary to repeatedly refresh the RAM at predetermined intervals of 2 msec or less. Otherwise, the data stored in the memory cells would be lost.
The memory cells of the dynamic RAM are usually arranged in a matrix form. To read data from, or write it into, one memory cell, a row address and a column address are supplied to the RAM chip. The row address designates the memory cells of one row. Items of data are read from these memory cells and stored in a buffer amplifier (refresh amplifier) provided within the RAM chip. The items of data stored in the buffer amplifier are written back into the memory cells of the row. Therefore, these memory cells on one row are refreshed every time a row address is supplied to the dynamic RAM. And the DRAM as a whole is refreshed after all the row addresses are supplied to the DRAM. In the case of a 4 K bit DRAM having a memory cell matrix of 64 rows by 64 columns, all the memory cells are completely refreshed when all the 64 row addresses are accessed.
The reading of display data from the video RAM is synchronized with the display of the data by the CRT display unit. If the items of data to be displayed are stored in a column of memory cells in the order of reading, the cells can be refreshed when the items of data are read to be displayed. A method of arranging bits forming a character code in the column of memory cells is described in Japanese Patent Disclosure No. 79-731.
This method is effective only for a certain format of the CRT screen in which the number of characters (digits) per display row is relatively large (e.g., 64 or 80 digits) and the number of rasters (scanning lines) per display row (one character) is relatively small (e.g., 8 or 10 rasters). When the CRT screen has 64 digits per row and 10 rasters per row, a time period for displaying one row is 640 .mu.sec if a display period for one raster is 64 .mu.sec. Therefore, three rows can be displayed in 2 msec. Hence, 192 (=64.times.3) character codes stored in VRAM are accessed within 2 msec. In other words, 192 different row addresses are accessed within 2 msec and a video RAM having less than 192 rows is refreshed within 2 msec.
Therefore, even if the video RAM is a dynamic RAM of 16 Kb (128 bits.times.128 bits), all memory cells can be refreshed within one refresh cycle of 2 msec.
However, a high-resolution display of characters is required for a personal computer; therefore, the number of rasters per row tends to increase and the number of digits per row tends to decrease. In this case, the prior art method has the following drawbacks. When the screen has 40 digits per row and 20 rasters per row, the period for displaying one row is 1.28 msec. Therefore, only 80 row addresses are accessed within 2.56 msec.